Japanese semiconductor manufacturer Rapidus announced on April 13 that its new semiconductor packaging process pilot line in Chitose City, Hokkaido, has officially started operation. This pilot line is a core part of the Rapidus Chiplet Solutions R&D facility, located within Seiko Epson's Chitose factory, with the aim of improving the production efficiency of AI chips.

Rapidus has adopted a new technology using square glass substrates measuring 600mm×600mm, which allows the number of intermediate layers produced per substrate to reach ten times that of the past. Through this method, Rapidus hopes to achieve significant efficiency improvements in AI chip production. In addition, Rapidus has also launched an analytical center adjacent to the 2nm wafer factory to perform real-time manufacturing and analysis closed-loop verification, ensuring product quality.

According to the company's plan, Rapidus aims to achieve mass production of 2nm process by the second half of the 2027 fiscal year, with an initial monthly capacity of 6,000 wafers, gradually increasing to 25,000 wafers. Achieving this goal will enable Rapidus to have stronger competitiveness in the semiconductor market.

In terms of financial support, on April 11, the Japanese Ministry of Economy, Trade and Industry approved an additional allocation of 631.5 billion yen to Rapidus, bringing the total government R&D support the company has received from 2022 to the 2026 fiscal year to 2.354 trillion yen. These funds will provide strong guarantees for Rapidus' technological research and development and production capacity enhancement.

Rapidus was jointly established by eight Japanese companies, including Toyota, Sony, and SoftBank, at the end of 2022, focusing on the research and production of next-generation semiconductors, aiming to secure a place in the global semiconductor market.