On February 3, 2026, Moore Threads, a leading domestic GPU company, officially launched the AI Coding Plan intelligent programming service. This service aims to completely revolutionize the software development model by combining domestic self-reliant computing power with advanced algorithms, further increasing the penetration rate of AI coding in China.

Core Technology: Deep Integration of Domestic Computing Power and Top Models

The intelligent programming service launched by Moore Threads has built a complete set of domestic technology stacks:

Hardware Foundation: Based on the domestic full-featured GPU MTT S5000, it provides underlying computing power support.

Inference Acceleration: Combined with the inference acceleration engine provided by Silicon Flow, it ensures smoothness and response speed of code generation.

Model-Driven: It uses the GLM-4.7 code model, giving the system powerful capabilities for code understanding, generation, and logical reasoning.

Market Prospects: Global Market Size Expected to Exceed $29.5 Billion by 2032

Changjiang Securities analysis points out that Moore Threads' service is expected to reshape the software development ecosystem and significantly improve productivity.

Penetration Growth: The current AI coding penetration rate in China is approximately 30%, and with the implementation of such domestic services, this figure is expected to enter an accelerated growth phase.

Vast Market Potential: It is expected that by 2032, the global AI Coding market size will exceed $29.5 billion.

Industry Response: Listed Companies Accelerate Layout in AI Programming

In addition to Moore Threads, several listed companies are also actively promoting AI programming solutions to improve development efficiency and application implementation speed:

Companies such as Sanwei Tian Di and Zhuoyi Information have successively launched related AI programming products.

Ecosystem Collaboration: Domestic GPU manufacturers and software service providers are jointly building a complete intelligent development loop from the underlying chip to the top-level application.